As the design of integrated circuits has progressed, more and more circuitry is being disposed in increasingly dense patterns and it has become correspondingly more difficult to test and diagnose such circuits. Several methodologies for performing integrated circuit testing use level sensitive scan design (LSSD) techniques to facilitate circuit testing and diagnosis. Integrated circuit devices of interest typically contain blocks of combinatorial logic paths whose inputs and outputs are supplied to certain memory elements. In an LSSD system, the memory elements are configurable to become shift register latches (SRLs). During test mode, these SRLs are capable of storing predetermined data patterns through a shifting operation. A plurality of SRLs can comprise a scan path with the output signals from the latch strings supplied to a signature register or multiple input signature register (MISR) for comparison and analysis with known results. During operation of the circuit in the normal system environment, the SRLs function as memory elements passing signals to be processed from one combinatorial block to another and at the same time typically receiving input signals for subsequent application to combinatorial logic blocks in subsequent clock cycles. The SRLs play a significant role in establishing and defining stable logic outputs at appropriate points in a machine cycle. Thus, the SRLs serve a dual purpose, one during test and one during normal system operation. Typically, one or more test clocks are supplied to the SRLs during system test. The operation of these clocks must be coordinated and tuned to exhibit the proper waveforms during system test in order to ensure accurate test results.
The scan operations and SRLs described above can be used to measure timing characteristics on an integrated circuit. Screening out integrated circuits with timing problems becomes essential as the number of integrated circuits that can pass low frequency tests but fail high frequency tests increases.